Graph Theoretical Problems in Next-Generation Chip Design

A major component of computer chip design is creating an optimal physical layout of a netlist, i.e., determining where to place the functional elements and how to route the wires connecting them when manufacturing a chip. Because of its basic structure, the overall problem of netlist layout contains many questions that lend themselves to graph theoretical modeling and analysis. We will describe the basic principles of netlist layout and present several graph theoretical questions inherent in the problem. Possible approaches to these questions include concepts from hypergraphs, graph partitioning, graph drawing, graph and geometric thickness, tree width, grid graphs, planar embeddings, and geometric graph theory.